
2002 Microchip Technology Inc.
DS41120B-page 107
PIC16C717/770/771
REGISTER 11-2:
A/D CONTROL REGISTER 1 (ADCON1: 9Fh)
The value that is in the ADRESH and ADRESL regis-
ters are not modified for a Power-on Reset. The
ADRESH and ADRESL registers will contain unknown
data after a Power-on Reset.
The A/D conversion results can be left justified (ADFM
bit cleared), or right justified (ADFM bit set).
data format of the PIC16C717/770/771.
FIGURE 11-1: PIC16C770/771 12-BIT A/D RESULT FORMATS
R/W-0
ADFM
VCFG2
VCFG1
VCFG0
Reserved
Reserved Reserved
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1
= Right justified
0
= Left justified
bit 6-4
VCFG<2:0>: Voltage Reference Configuration bits
bit 3-0
Reserved: Do not use.
Note 1: This parameter is VDD for the PIC16C717.
2: This parameter is VSS for the PIC16C717.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
A/D VREF+A/D VREF-
000
AVDD(1)
AVSS(2)
001
External VREF+
External VREF-
010
Internal VRH
Internal VRL
011
External VREF+AVSS(2)
100
Internal VRH
AVSS(2)
101
AVDD(1)
External VREF-
110
AVDD(1)
Internal VRL
111
Internal VRL
AVSS
ADRESH (1Eh)
ADRESL (9Eh)
Left Justified
(ADFM = 0)
MSB
LSB
bit7
12-bit A/D Result
Unused
Right Justified
(ADFM = 1)
MSB
LSB
bit7
Unused
12-bit A/D Result